Digital-to-Analog Converter

ABSTRACT

A PRA-DAC is disclosed. The PRA-DAC is operable to increase its conversion speed.

TECHNICAL FIELD

The subject matter of this specification is generally related to digital-to-analog converters.

BACKGROUND

A digital-to-analog converter (DAC) is a device for converting a digital code to an analog signal. For example, a DAC can convert an 8-bit digital signal into an output voltage or current having an amplitude representing the digital code. Two common examples of DACs are the “R-string” DAC and the “R-2R ladder” DAC. Another example is the parallel resistors architecture (PRA) DAC. Advantages of the PRA-DAC over the “R-string” DAC and the “R-2R ladder” DAC include that the PRA-DAC has a constant output impedance and inherent monotonicity compared to “R-2R ladder” DACs.

When an input (e.g., a digital code) is changed, the output (e.g., an analog signal) of a DAC settles to a value after a delay called a settling time. The settling time depends on the output resistance Rout of the DAC and a capacitive load CL at the output of the DAC. In particular, the settling time depends on a time constant that can be defined by the product of Rout and CL. The settling time can limit a conversion speed of the DAC.

SUMMARY

A PRA-DAC is disclosed. The PRA-DAC is operable to increase its conversion speed.

An advantage of the PRA-DAC is that its conversion speed can be increased (i) without affecting resistor matching, thereby maintaining the linearity of the PRA-DAC; and (ii) without increasing power consumption during a period of fine settling.

DESCRIPTION OF DRAWINGS

FIG. 1 is a schematic circuit diagram illustrating an example PRA-DAC.

FIG. 2 is a diagram including example resistance values of adjustable resistive elements in the PRA-DAC of FIG. 1.

FIG. 3 is a diagram illustrating example settling times.

Like reference symbols in the various drawings indicate like elements.

DETAILED DESCRIPTION Example PRA-DAC

FIG. 1 is a schematic circuit diagram illustrating an example PRA-DAC 100. In this example, the PRA-DAC 100 is an N-bit DAC that receives a digital input D having N bits (e.g., d₀, d₁, . . . , d_(N-1)). Based on a received D, the PRA-DAC 100 generates an analog voltage output Vout. In one example, Vout can increase monotonically with D. For example, if D₁>D₂, Vout_(D1)>Vout_(D2).

The PRA-DAC 100 includes a resistive network. The resistive network includes 2^(N) sets of parallel resistive elements 110. In some implementations, a capacitive load CL can be coupled to the resistive network at the output of the PRA-DAC 100. In this example, each of the sets of parallel resistive elements 110 includes a resistive element RA and a resistive element RB. The sets of parallel resistive elements 110 have substantially the same resistance R=RA+RB. One of the sets of parallel resistive elements 110 a is connected to ground GND. 2^(N)−1 of the sets of parallel resistive elements 110 b are coupled to a first switch network. The first switch network includes switches S1, S2, . . . , S2 ^(N)−1. S1 to S2 ^(N)−1 can control the 2^(N)−1 sets of parallel resistive elements 110 b to be connected either to a reference voltage Vref or to GND.

S1 to S2 ^(N)−1 connect the sets of parallel resistive elements 110 b based on a control word generated by a decoder 120. For example, S1 to S2 ^(N)−1 can be configured so that a switch connects a connected resistor to Vref if a control signal representing logic 1 is received, and the switch connects the connected resistor to GND if a control signal representing logic 0 is received. Other reference levels can also be used. In some implementations, a switch can be a transistor that is biased to behave like a switch. Other implementations are possible.

The decoder 120 generates a 2^(N)−1 bits control word based on the received D. In some implementations, each control bit in the control word corresponds to one of the switches of S1 to S2 ^(N)−1. Based on the corresponding control bit, S1 to S2 ^(N)−1 can connect the sets of parallel resistive elements 110 b to Vref or GND. In some implementations, the control word can be a decoded representation of D. For a given D (e.g., D is an integer between 0 and 2^(N)−1), D of the 2^(N)−1 control bits may be at logic 1 and 2^(N)−D of the control bits may be at logic 0. In some implementations, because the decoder 120 is configured to generate D of the 2^(N)−1 control signals at logic 1, D of the sets of parallel resistive elements 110 are connected to Vref and 2^(N)−D resistors are connected to GND.

Accordingly, the PRA-DAC 100 can generate Vout based on a voltage division between the sets of parallel resistive elements 110 connected to Vref and the sets of parallel resistive elements 110 connected to GND. In some implementations, the equivalent resistance between Vref and Vout is approximately

$\frac{R}{D},$

and the equivalent resistance between Vout and GND is approximately

$\frac{R}{2^{N} - D}.$

The PRA-DAC 100 can generate Vout based on D (Vout(D)) according to the following equation:

${{Vout}(D)} = {D \cdot {\frac{Vref}{2^{N}}.}}$

The PRA-DAC 100 can generate Vout(D) that is substantially monotonic to D. For example, as D is incremented by one (e.g., increment from D to D+1), an additional resistive element is connected to Vref. Thus, Vout(D) is less than Vout(D+1). In some implementations, the monotonic property of the PRA-DAC 100 is substantially independent of the quality of the matching of the sets of parallel resistive elements 110. For example, if the sets of parallel resistive elements 110 are poorly matched, resulting in highly varied resistance across the sets of parallel resistive elements 110, the monotonic property of the PRA-DAC 100 can still be substantially preserved because more resistance is still connected to Vref.

As shown, the PRA-DAC 100 draws a reference current Iref from Vref. In this example, Iref flows first from a node at Vref to a node at Vout through D sets of parallel resistive elements 110, and then from Vout to GND through 2^(N)−D sets of parallel resistive elements 110. Depending on D, Iref(D) can be expressed as:

${{{Iref}(D)} = {\frac{D}{R} \cdot \left( {{Vref} - {{Vout}(D)}} \right)}},{and}$ ${{Iref}(D)} = {\frac{2^{N} - D}{R} \cdot {{{Vout}(D)}.}}$

From the above equations, Iref(D) can be expressed as:

${{Iref}(D)} = {\frac{Vref}{\frac{R}{D} + \frac{R}{2^{N} - D}}.}$

By rearranging the above equation, Iref(D) can be expressed as:

${{{Iref}(D)} = {D \cdot \left( {2^{N} - D} \right) \cdot \frac{Vref}{2^{N} \cdot R}}},{or}$ ${{{Iref}(D)} = {D \cdot \left( {2^{N} - D} \right) \cdot \frac{LSB}{R}}},{where}$ ${LSB} = {\frac{Vref}{2^{N}}.}$

Note that Iref(D) is a second order polynomial depending on D. Iref(D) is at a minimum at D=0. The minimum value of Iref(D) is:

I _(min) =Iref(D=0)=0.

At mid-scale (2^(N-1)), Iref(D) increases to a maximum. The maximum value of Iref(D) is:

$I_{\max} = {{{Iref}\left( {D = 2^{N - 1}} \right)} = {{2^{N - 2} \cdot \frac{Vref}{R}} = {2^{{2N} - 2} \cdot {\frac{LSB}{R}.}}}}$

After mid-scale, Iref(D) symmetrically decreases to:

${{Iref}\left( {D = {2^{N} - 1}} \right)} = {\frac{2^{N} - 1}{2^{N}} \cdot {\frac{Vref}{R}.}}$

The output resistance of the PRA-DAC 100 at D (Rout(D)) includes the resistance

$\frac{R}{D}$

in parallel with

$\frac{R}{2^{N} - D}.$

Solving for the equivalent resistance, Rout(D) can be expressed as

${{{Rout}(D)} = \frac{R}{2^{N}}},$

where Rout is independent of D.

Settling Time and Conversion Speed

When D changes, Vout(D) settles to a value (e.g., a final value) after a delay called the settling time t_(SETTLE). For example, Vout(D) can be considered to have settled to its final value, when Vout(D) is less than

$\frac{LSB}{2}$

away from

${D \cdot \frac{Vref}{2^{N}}}\mspace{14mu} {\left( {{e.g.},{{{{{Vout}(D)} - \left( {D \cdot \frac{Vref}{2^{N}}} \right)}} < \frac{LSB}{2}}} \right).}$

Because a conversion speed f_(S) of the PRA-DAC 100 (e.g., a rate at which D changes) depends on t_(SETTLE), f_(S) cannot be greater than

$\frac{1}{t_{SETTLE}}.$

For example, depending on the rate at which D changes, Vout(D) at

$T_{S} = \frac{1}{f_{S}}$

(e.g., a period of D) can be greater than

$\frac{LSB}{2}$

away from

${D \cdot \frac{Vref}{2^{N}}}{\left( {{e.g.},{{{{{Vout}(D)} - \left( {D \cdot \frac{Vref}{2^{N}}} \right)}} > \frac{LSB}{2}}} \right).}$

Thus, a maximum value of f_(S) can be expressed as:

$f_{S\_ MAX} = {\frac{1}{t_{SETTLE}}.}$

As explained previously, t_(SETTLE) depends on τ_(DAC). τ_(DAC) can be expressed as:

$\tau_{DAC} = {{{Rout} \cdot {CL}} = {\frac{R}{2^{N}} \cdot {{CL}.}}}$

For a first order system, Vout(D) settles exponentially and can be expressed as:

${{Vout}(t)} = {{{Vout}\left( {t = 0} \right)} + {\left\lbrack {{{Vout}\left( {t = \infty} \right)} - {{Vout}\left( {t = 0} \right)}} \right\rbrack \cdot {\left\lbrack {1 - {\exp \left( {- \frac{t}{\tau_{DAC}}} \right)}} \right\rbrack.}}}$

Vout(t) at t=τ_(DAC) can be expressed as:

$\begin{matrix} {{{Vout}\left( {t = \tau_{DAC}} \right)} = {{{Vout}\left( {t = 0} \right)} + {\left\lbrack {{{Vout}\left( {t = \infty} \right)} - {{Vout}\left( {t = 0} \right)}} \right\rbrack \cdot {\left\lbrack {1 - {\exp \left( {- \frac{\tau_{DAC}}{\tau_{DAC}}} \right)}} \right\rbrack.}}}} & {{Expression}\mspace{20mu}\lbrack 1\rbrack} \end{matrix}$

Simplifying, Vout(t=τ_(DAC)) can be expressed as:

Vout(t=τ _(DAC))≈Vout(t=0)+0.63·[Vout(t=∞)−Vout(t=0)].

For a first order system, the relationship between t_(SETTLE) and τ_(DAC) can also depend on N. Again, Vout(D) can be considered to have settled to its final value when Vout(D) is less than

$\frac{LSB}{2}$

away from

$D \cdot {\frac{Vref}{2^{N}}.}$

This condition can also be expressed as:

$\begin{matrix} {{{{{Vout}\left( {t = \infty} \right)} - {{Vout}\left( {t = t_{SETTLE}} \right)}} < \frac{LSB}{2}} = {\frac{Vref}{2^{N + 1}}.}} & {{Expression}\mspace{20mu}\lbrack 2\rbrack} \end{matrix}$

Generally, Vout(t=0)=0 and Vout(t=∞)=Vref. Using Expression [1], Vout(t) can be expressed as:

$\begin{matrix} {{{Vout}(t)} = {{Vref} \cdot {\left\lbrack {1 - {\exp \left( {- \frac{t}{\tau_{DAC}}} \right)}} \right\rbrack.}}} & {{Expression}\mspace{20mu}\lbrack 3\rbrack} \end{matrix}$

Using Expression [3] and Expression [2], the condition can be expressed as:

${{{Vref} - {{Vref} \cdot \left\lbrack {1 - {\exp \left( {- \frac{t_{SETTLE}}{\tau_{DAC}}} \right)}} \right\rbrack}} < \frac{Vref}{2^{N + 1}}},{or}$ ${\exp \left( {- \frac{t_{SETTLE}}{\tau_{DAC}}} \right)} < {\frac{1}{2^{N + 1}}.}$

Using the neperian logarithm, the condition can be expressed as:

${{\ln \left\lbrack {\exp \left( {- \frac{t_{SETTLE}}{\tau_{DAC}}} \right)} \right\rbrack} < {\ln \left\lbrack \frac{1}{2^{N + 1}} \right\rbrack}},{{{or} - \frac{t_{SETTLE}}{\tau_{DAC}}} < {{- \left( {N + 1} \right)} \cdot {{\ln (2)}.}}}$

Therefore, the condition can be expressed as:

t_(SETTLE) > (N + 1) ⋅ ln (2) ⋅ τ_(DAC), t_(SETTLE) > (N + 1) ⋅ ln (2) ⋅ Rout ⋅ CL, or $t_{SETTLE} > {\left( {N + 1} \right) \cdot {\ln (2)} \cdot \frac{R}{2^{N}} \cdot {{CL}.}}$

Conversion Speed of the Example PRA-DAC

As discussed previously, f_(S) depends on t_(SETTLE), t_(SETTLE) depends on τ_(DAC), and τ_(DAC) depends on Rout. Therefore t_(SETTLE) can be reduced by reducing Rout of the PRA-DAC 100. Permanently reducing Rout can result in increased power consumption that can be proportional to the reduction in Rout. Furthermore, reducing resistances of resistive elements in the PRA-DAC, for example, can decrease the quality of resistor matching (e.g., matching actual resistance values among the sets of parallel resistive elements 110, including the actual resistance values of RA and RB). For example, in various embodiments, the actual resistance values of the resistors RA (e.g., RA coupled to S1, RA coupled to S2, and RA coupled to S3, etc.) are preferably matched, or substantially the same value. As another example, the actual resistance values of the resistors RB (e.g., RB coupled to S1′, RB coupled to S2′, and RB coupled to S3′, etc.) are preferably matched, or substantially the same value.

If the resistances of the resistive elements are reduced, the resistor matching can become, for example, more susceptible to parasitic resistances (e.g., parasitic resistances of switches and metal routings between resistors). Because the actual resistances of the sets of parallel resistive elements 110 may not be substantially the same value, voltage division between the sets of parallel resistive elements 110 connected to Vref, for example, can vary, thereby affecting Vout. The linearity of the PRA-DAC 100 can be decreased because the linearity depends on the resistor matching.

Referring to FIG. 1, the PRA-DAC 100 is operable to temporarily reduce Rout. A first input signal PHI1 (e.g., a clock signal), received at the decoder 120, can set f_(S). The resistive elements RA in the sets of parallel resistive elements 110 can be coupled to a second switch network. The second switch network includes switches S0′, S1′, S2′, . . . , S(2 ^(N)−1)′. The second switch network is operable to short the resistive elements RA in response to a second input signal PHI2. For example, when PHI2 is high (e.g., represented by logic 1), the second switch network can short the resistive elements RA. Alternatively, when PHI2 is low (e.g., represented by logic 0), the second switch network is open. Other reference levels can be used.

When the second switch network is open, the sets of parallel resistive elements 110 have a resistance R=RA+RB. Shorting the resistive elements RA causes the sets of parallel resistive elements 110 to have a resistance R=RB. Because

${{{Rout}(D)} = \frac{R}{2^{N}}},$

Rout is reduced. Thus, τ_(DAC) and t_(SETTLE) are reduced, and f_(S) can be increased.

FIG. 2 is a diagram 200 including example resistance values of adjustable resistive elements in the PRA-DAC of FIG. 1. The diagram 200 also includes a control signal S that is used to operate (e.g., open and close) S1 to S2 ^(N)−1 of FIG. 1. As shown in FIG. 2, PHI1 can be used to temporarily reduce Rout.

PHI2 can depend on PHI1. In particular, PHI2 can be high for a first portion of a clock period of PHI1. The first portion can correspond to a period of coarse settling, where R=B. During coarse settling, Vout(t) settles with a corresponding time constant

$\tau_{{DAC}\; 1} = {\frac{RB}{2^{N} \cdot {CL}}.}$

The first portion of PHI2 can be followed by a second portion of the clock period of PHI1, where PHI2 is low. The second portion corresponds to a period of fine settling, where R=RA+RB. During fine settling, Vout(t) settles with a corresponding time constant

$\tau_{{DAC}\; 2} = {\frac{{RA} + {RB}}{2^{N} \cdot {CL}}.}$

Because Rout is temporarily reduced during the first portion of the clock period of PHI1, τ_(DAC) and t_(SETTLE) can be reduced during the first portion of the clock period of PHI1. Furthermore, because R can equal (RA+RB) during a second portion of the clock period of PHI1, the linearity of the PRA-DAC 100 can be maintained during the second portion of the clock period of PHI1. Furthermore, increased power consumption of the PRA-DAC 100 can be limited to the first portion of the clock period of PHI1.

FIG. 3 is a diagram 300 illustrating example settling times. In particular, FIG. 3 illustrates example settling times for a PRA-DAC where

${RB} = {\frac{1}{2}{{RA}.}}$

Therefore,

$\tau_{{DAC}\; 1} = \frac{RB}{2^{N} \cdot {CL}}$ and $\tau_{{DAC}\; 2} = {\frac{{RA} + {RB}}{2^{N} \cdot {CL}} = {\frac{3 \cdot {RB}}{2^{N} \cdot {CL}}.}}$

When Rout is temporarily reduced, Vout settles to approximately 63% of a final value at t=τ_(DAC1) (e.g., as illustrated by plot 310) approximately three times faster than when Rout is not temporarily reduced (e.g., as illustrated by plot 320 at t=τ_(DAC2)). In addition, when Rout is temporarily reduced, t_(SETTLE1)<t_(SETTLE2).

In the example, PHI2 has been configured so that a period of coarse settling equals to τ_(DAC1). After the coarse settling, a period of fine settling follows that corresponds to τ_(DAC2). In some implementations, PHI2 can be generated so that PHI2 is high for the entire clock period of PHI1. Other configurations are possible.

Although one implementation of a PRA-DAC (e.g., the PRA-DAC 100 of FIG. 1) is described, other implementations are also possible. For example, the PRA-DAC can include other architectures that allow the PRA-DAC to temporarily reduce Rout. For example, other types of resistive elements (e.g., transistors) can be used. As another example, the resistive elements of the PRA-DAC can be adjustable resistive elements (e.g., variable resistors). As another example, the sets of parallel resistive elements 110 of FIG. 1 can alternatively include switched resistors in parallel.

A number of implementations of the invention have been described. Nevertheless, it will be understood that various modifications may be made without departing from the spirit and scope of the invention. Accordingly, other implementations are within the scope of the following claims. 

1. A digital-to-analog converter (DAC) comprising: a resistive network including a set of resistive elements, the resistive network having a first resistance for a first portion of a settling time of the DAC determined at least by a capacitive load and the first resistance, and a second resistance for a second portion of the settling time of the DAC determined at least by the capacitive load and the second resistance, wherein the second resistance is greater than the first resistance; and a first switch network coupled to the set of resistive elements and operable to select one or more resistive elements from the set of resistive elements in response to a first input signal and a control signal.
 2. The DAC of claim 1, wherein the second portion follows the first portion.
 3. The DAC of claim 1, wherein the set of resistive elements includes subsets of resistive elements that each include a first resistive element coupled in series to a second resistive element, the second resistive element coupled in parallel to a second switch network that is operable to receive a second input signal and short the second resistive element for the first portion of the settling time.
 4. The DAC of claim 1, wherein the set of resistive elements includes a first subset of resistive elements and a second subset of resistive elements, the second subset of resistive elements coupled to a second switch network that is operable to switch the resistive network between the first resistance and the second resistance in response to a second input signal.
 5. The DAC of claim 4, wherein the second input signal depends on the first input signal.
 6. The DAC of claim 1, wherein the resistive network is operable to be coupled to the capacitive load.
 7. The DAC of claim 6, wherein the settling time of the DAC is equal to a product of an output resistance of the DAC and a capacitance of the capacitive load.
 8. The DAC of claim 1, further comprising: a decoder coupled to the first switch network and operable to generate the control signal.
 9. A method comprising: selecting one or more resistive elements from a first set of resistive elements in a resistive network of a digital-to-analog converter (DAC), in response to a first input signal and a control signal; and switching a resistance of the resistive network from a first resistance for a first portion of a settling time of the DAC determined at least by a capacitive load and the first resistance to a second resistance for a second portion of the settling time of the DAC determined at least by a capacitive load and the second resistance, wherein the second resistance is greater than the first resistance.
 10. The method of claim 9, wherein the second portion follows the first portion.
 11. The method of claim 9, wherein switching a resistance of the resistive network comprises: shorting a subset of resistive elements in the first set of resistive elements in response to a second input signal.
 12. The method of claim 9, wherein the settling time of the DAC is equal to a product of an output resistance of the DAC and a capacitance of the capacitive load coupled to the DAC.
 13. A digital-to-analog converter (DAC) comprising: a resistive network including a first set of resistive elements; and a first switch network coupled to the resistive network and operable to select one or more resistive elements from the first set of resistive elements in response to a first input signal and a control signal, wherein the first set of resistive elements has an adjustable resistance that is operable to temporarily reduce an output resistance of the DAC.
 14. The DAC of claim 13, wherein the resistive network is operable to be coupled to a capacitive load.
 15. The DAC of claim 14, wherein a settling time of the DAC is equal to a product of the output resistance of the DAC and a capacitance of the capacitive load.
 16. The DAC of claim 13, wherein the first set of resistive elements includes resistive elements having a variable resistance.
 17. The DAC of claim 13, wherein the first set of resistive elements includes subsets of resistive elements that each include a first resistive element coupled in series to a second resistive element, the second resistive element coupled in parallel to a second switch network that is operable to receive a second input signal and short the second resistive element.
 18. The DAC of claim 13, further comprising: a decoder coupled to the first switch network and operable to generate the control signal. 